參數(shù)資料
型號(hào)： UPD780033AYGK
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 45/70頁(yè)
文件大?。?/td> 527K
代理商： UPD780033AYGK
45
μ
PD780031AY, 780032AY, 780033AY, 780034AY
Data Sheet U14045EJ1V0DS00
(2) Read/Write Operation (T
A
= –40 to + 85
°
C, V
DD
= 1.8 to 2.7 V)
(3/3)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.3t
CY
ns
Address setup time
t
ADS
120
ns
Address hold time
t
ADH
20
ns
Data input time from address
t
ADD1
(2 + 2n)t
CY
– 233
ns
t
ADD2
(3 + 2n)t
CY
– 240
ns
Address output time from RD
↓
t
RDAD
0
400
ns
Data input time from RD
↓
t
RDD1
(2 + 2n)t
CY
– 325
ns
t
RDD2
(3 + 2n)t
CY
– 332
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.5 + 2n)t
CY
– 92
ns
t
RDL2
(2.5 + 2n)t
CY
– 92
ns
WAIT
↓
input time from RD
↓
t
RDWT1
t
CY
– 350
ns
t
RDWT2
t
CY
– 132
ns
WAIT
↓
input time from WR
↓
t
WRWT
t
CY
– 100
ns
WAIT low-level width
t
WTL
(0.5 + 2n)t
CY
+ 10
(2 + 2n)t
CY
ns
Write data setup time
t
WDS
60
ns
Write data hold time
t
WDH
20
ns
WR low-level width
t
WRL1
(1.5 + 2n)t
CY
– 60
ns
RD
↓
delay time from ASTB
↓
t
ASTRD
20
ns
WR
↓
delay time from ASTB
↓
t
ASTWR
2t
CY
– 60
ns
ASTB
↑
delay time from
RD
↑
at external fetch
t
RDAST
0.8t
CY
– 60
1.2t
CY
ns
Address hold time from
RD
↑
at external fetch
t
RDADH
0.8t
CY
– 60
1.2t
CY
+ 120
ns
Write data output time from RD
↑
t
RDWD
40
ns
Write data output time from WR
↓
t
WRWD
40
240
ns
Address hold time from WR
↑
t
WRADH
0.8t
CY
– 60
1.2t
CY
+ 120
ns
RD
↑
delay time from WAIT
↑
t
WTRD
0.5t
CY
2.5t
CY
+ 100
ns
WR
↑
delay time from WAIT
↑
t
WTWR
0.5t
CY
2.5t
CY
+ 100
ns
Remarks
1.
2.
3.
t
CY
= T
CY
/4
n indicates the number of waits.
C
L
= 100pF (C
L
indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and
ASTB pins.)
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