參數(shù)資料
型號： UPD780031AYCW(A)-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù)： 61/94頁
文件大?。?/td> 682K
代理商： UPD780031AYCW(A)-XXX
64
PD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
Data Sheet U15132EJ2V0DS
(2) Read/Write Operation (TA = –40 to +85
°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
Address output time from RD
↓
tRDAD
0
100
ns
Data input time from RD
↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD
↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
Input time from WR
↓ to WAIT↓
tWRWT
tCY – 25
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
(2 + 2n)tCY
ns
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB
↓ to RD↓
tASTRD
6ns
Delay time from ASTB
↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
RD
↑ to ASTB↑ at external fetch
Address hold time from
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
RD
↑ at external fetch
Write data output time from RD
↑
tRDWD
40
ns
Write data output time from WR
↓
tWRWD
10
60
ns
Address hold time from WR
↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT
↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT
↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
Caution
TCY can only be used when the MIN. value is 0.238
s.
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
(1/3)
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