參數(shù)資料
型號： UPD780021AYGC-XXX-8BS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, PLASTIC, LQFP-64
文件頁數(shù)： 64/96頁
文件大小： 723K
代理商： UPD780021AYGC-XXX-8BS
67
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
(3) Serial Interface (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK3n
tKCY1
4.0 V
≤ VDD ≤ 5.5 V
954
ns
cycle time
2.7 V
≤ VDD < 4.0 V
1600
ns
1.8 V
≤ VDD < 2.7 V
3200
ns
SCK3n high-/
tKH1, tKL1
4.0 V
≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
low-level width
1.8 V
≤ VDD < 4.0 V
tKCY1/2 – 100
ns
SI3n setup time
tSIK1
4.0 V
≤ VDD ≤ 5.5 V
100
ns
(to SCK3n
↑)
2.7 V
≤ VDD < 4.0 V
150
ns
1.8 V
≤ VDD < 2.7 V
300
ns
SI3n hold time
tKSI1
400
ns
(from SCK3n
↑)
Delay time from
tKSO1
C = 100 pF
Note
300
ns
SCK3n
↓ to SO3n
output
Note C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK3n
4.0 V
≤ VDD ≤ 5.5 V
800
ns
cycle time
2.7 V
≤ VDD < 4.0 V
1600
ns
1.8 V
≤ VDD < 2.7 V
3200
ns
SCK3n high-/
tKH2, tKL2
4.0 V
≤ VDD ≤ 5.5 V
400
ns
low-level width
2.7 V
≤ VDD < 4.0 V
800
ns
1.8 V
≤ VDD < 2.7 V
1600
ns
SI3n setup time
tSIK2
100
ns
(to SCK3n
↑)
SI3n hold time
tKSI2
400
ns
(from SCK3n
↑)
Delay time from
tKSO2
C = 100 pF
Note
300
ns
SCK3n
↓ to SO3n
output
Note C is the load capacitance of the SO3n output line.
Remark
Conventional products of
PD780021A, 780022A, 780023A, 780024A: n = 0 or 1
PD780021AY, 780022AY, 780023AY, 780024AY: n = 0
tKCY2
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