參數(shù)資料
型號: UPD75006
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機
文件頁數(shù): 48/66頁
文件大?。?/td> 542K
代理商: UPD75006
μ
PD75004, 75006, 75008
48
SBI MODE (SCK: internal clock output (master)):
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK Cycle Time
t
KCY3
V
DD
= 4.5 to 6.0 V
1600
3800
t
KCY3
/2-50
ns
ns
ns
SCK High-, Low-Level
Widths
t
KL3
t
KH3
V
DD
= 4.5 to 6.0 V
t
KCY3
/2-150
ns
SB0, 1 Set-Up Time
(vs. SCK
)
SB0, 1 Hold Time
(vs. SCK
)
SCK
↓→
SB0, 1 Output
Delay Time
t
SIK3
150
ns
t
KSI3
t
KCY3
/2
ns
t
KSO3
R
= 1 k
,
C
= 100 pF*
V
DD
= 4.5 to 6.0 V
0
250
ns
0
1000
ns
ns
ns
ns
SCK
↑→
SB0, 1
SB0,1
↓→
SCK
SB0, 1 Low-Level Width
t
KSB
t
SBK
t
SBL
t
KCY3
t
KCY3
t
KCY3
SB0, 1 High-Level Width
t
SBH
t
KCY3
ns
SBI MODE (SCK: external clock input (slave)):
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK Cycle Time
t
KCY4
V
DD
= 4.5 to 6.0 V
800
3200
400
ns
ns
ns
SCK High-, Low-Level
Widths
t
KL4
t
KH4
V
DD
= 4.5 to 6.0 V
1600
ns
SB0, 1 Set-Up Time
(vs. SCK
)
SB0, 1 Hold Time
(vs. SCK
)
SCK
↓→
SB0, 1 Output
Delay Time
t
SIK4
100
ns
t
KSI4
t
KCY4
/2
ns
t
KSO4
R
= 1 k
,
C
= 100 pF*
V
DD
= 4.5 to 6.0 V
0
300
ns
0
1000
ns
ns
ns
ns
SCK
↑→
SB0, 1
SB0,1
↓→
SCK
SB0, 1 Low-Level Width
t
KSB
t
SBK
t
SBL
t
KCY4
t
KCY4
t
KCY4
SB0, 1 High-Level Width
t
SBH
t
KCY4
ns
*: R and C are load resistance and load capacitance of the SB0 and SB1 output lines.
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