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參數(shù)資料
| 型號(hào)： | UPD75004 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 31/66頁(yè) |
| 文件大小： | 542K |
| 代理商： | UPD75004 |
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μ
PD75004, 75006, 75008
31
8. RESET FUNCTION
When the RESET signal is input, the
μ
PD75008 is reset and each hardware is initialized as indicated in Table
8-1. Fig. 8-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware
RESET Input in Standby Mode
RESET Input during Operation
Program Counter (PC)
The contents of the lower 4 bits
of address 000H of the program
memory are set to PC11-8, and
the contents of address 001H are
set to PC7-0.
Same as at left
PSW
Carry Flag (CY)
Retained
Undefined
Skip Flag (SK0-2)
0
0
Interrupt Status Flag (IST0)
0
0
Bank Enable Flag (MBE)
The contents of bit 7 of address
000H of the program memory is
set to MBE.
Same as at left
Stack Pointer (SP)
Undefined
Undefined
Data Memory (RAM)
General-Purpose Register
(X, A, H, L, D, E, B, C)
Retained
Undefined
Bank Selection Register (MBS)
0
Undefined
Timer/Event
Counter
Counter (T0)
0
0
Module Register
(TMOD0)
Mode Register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Mode Register (BTM)
0
0
Mode Register (WM)
0
Watch Timer
0
*
Basic Interval
Timer
Counter (BT)
0
Undefined
*
: Data of address 0F8H to 0FDH of the data memory becomes undefined when a
RESET
signal is input.
Retained
Undefined
FFH
FFH
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