參數(shù)資料
型號(hào): UPD720110AGC-8EA
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 19/32頁
文件大?。?/td> 405K
代理商: UPD720110AGC-8EA
Data Sheet S15737EJ5V0DS
19
μ
PD720110A
(4/4)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Hub Event Timings (Continued)
Inter-packet delay for full-speed
t
IPD
2
Bit
times
Inter-packet delay for device response with
detachable cable for full-speed
t
RSPIPD1
6.5
Bit
times
SetAddress() completion time
t
DSETADDR
50
ms
Time to complete standard request with no
data
t
DRQCMPLTND
50
ms
Time to deliver first and subsequent
(except last) data for standard request
t
DRETDATA1
500
ms
Time to deliver last data for standard
request
t
DRETDATAN
50
ms
Time for which a suspended hub will see a
continuous SE0 on upstream before
beginning the high-speed detection
handshake
t
FILTSE0
2.5
μ
s
Time a hub operating in non-suspended
full-speed will wait after start of SE0 on
upstream before beginning the high-speed
detection handshake
t
WTRSTFS
2.5
3000
ms
Time a hub operating in high-speed will
wait after start of SE0 on upstream before
reverting to full-speed
t
WTREV
3.0
3.125
ms
Time a hub will wait after reverting to full-
speed before sampling the bus state on
upstream and beginning the high-speed
will wait after start of SE0 on upstream
before reverting to full-speed
t
WTRSTHS
100
875
ms
Minimum duration of a Chirp K on
upstream from a hub within the reset
protocol
t
UCH
1.0
ms
Time after start of SE0 on upstream by
which a hub will complete its Chirp K within
the reset protocol
t
UCHEND
7.0
ms
Time between detection of downstream
chip and entering high-speed state
t
WTHS
500
μ
s
Time after end of upstream Chirp at which
hub reverts to full-speed default state if no
downstream Chirp is detected
t
WTFS
1.0
2.5
ms
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