參數(shù)資料
型號(hào)： UPD70F3107AGJA-UEN
廠商： NEC Corp.
英文描述： 32-Bit Single-Chip Microcontrollers
中文描述： 32位單芯片微控制器
文件頁(yè)數(shù)： 38/99頁(yè)
文件大?。?/td> 528K
代理商： UPD70F3107AGJA-UEN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
38
3.4.4 PCI_IO_BASE register
When I/O accessing the PCI bus I/O space via the PCI I/O area (area in which the I_CPU_CS1_B pin becomes
active: 64 KB), any area of the 4 GB PCI bus I/O space can be accessed by setting this register.
After reset: 00000000H R/W Offset address: 10H
31
16 15
0
IO_BASE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
Function
IO_BASE
R/W
Sets the higher 16 bits (bits 16 to 31) of the PCI bus I/O space base address when accessing the
PCI I/O area (area in which the I_CPU_CS1_B pin becomes active) from the CPU.
3.4.5 PCI_MEM_BASE register
When memory accessing the PCI bus memory space via the PCI memory area (area in which the I_CPU_CS2_B
pin becomes active: 1 MB), any area of the 4 GB PCI bus memory space can be accessed by setting this register.
However, because the main memory (SDRAM) is mapped on the PCI bus memory space, do not overlap the area
set by the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register described later.
After reset: 80000000H R/W Offset address: 14H
31
20 19
0
M_BASE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
Function
M_BASE
R/W
Sets the higher 12 bits (bits 20 to 31) of the PCI bus memory space base address when accessing
the PCI memory area (area in which the I_CPU_CS2_B pin becomes active) from the CPU.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD70F3107AGJ-UEN 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD70F3107AGJ-UEN-A 制造商:Renesas Electronics 功能描述:V850 50MHz 制造商:Renesas Electronics 功能描述:V850 50MHz Cut Tape
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UPD70F3107GJ-UEN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
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