
CHAPTER 7 TIMER/COUNTER FUNCTION
User’s Manual U12768EJ4V1UD
173
(3) Pulse width measurement with free running counter and two capture registers
When 16-bit timer register n (TMn) is used as a free running counter (refer to Figure 7-19), the pulse width of the
signal input to the TIn0 pin can be measured.
When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n (PRMn) is input to the
TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt
request signal (INTTMn1) is set.
The value of TMn is also loaded to 16-bit capture/compare register n0 (CRn0) when an edge reverse to the one
that triggers capturing to CRn1 is input.
The edge of the TIn0 pin is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n (PRMn).
The rising or falling edge can be eliminated.
The valid edge of TIn0 is detected by sampling at the count clock cycle selected by prescaler mode register n, n1
(PRMn, PRMn1), and the capture operation is not performed until the valid level is detected two times.
Therefore, noise with a short pulse width can be eliminated.
Caution
If the valid edge of the TIn0 pin is specified to be both the rising and falling edges,
capture/compare register n0 (CRn0) cannot perform its capture operation.
Remark
n = 0, 1
Figure 7-12. Control Register Settings for Pulse Width Measurement
with Free-Running Counter and Two Capture Registers
(a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3
TMCn2
TMCn1
OVFn
TMCn
0
1
0/1
0
Free-running mode
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2
CRCn1
CRCn0
CRCn
0
1
CRn0 used as capture
register
Captures to CRn0 at
edge reverse to valid
edge of TIn0 pin.
CRn1 used as capture
register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse
width measurement function.
For details, refer to 7.1.4 (1) 16-bit timer mode control
registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0,
CRC1).