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參數(shù)資料
| 型號： | UPD6600AGS |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION |
| 中文描述： | 4位單片機(jī)的遙控傳輸 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大小： | 172K |
| 代理商： | UPD6600AGS |
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μ
PD6124A, 6600A
15
14. STANDBY FUNCTION (HALT INSTRUCTION)
The
μ
PD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,
when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).
In the standby mode, the program execution stops. However, the contents of the internal registers and the data
memory are all retained.
14.1
STOP MODE (OSCILLATION STOP HALT INSTRUCTION)
In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops.
Therefore, operations requiring the system clock will stop.
If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode
will be initiated, after the timer count down operation is completed.
14.2
HALT MODE (OSCILLATION CONTINUE HALT INSTRUCTION)
The CPU stops its operation, until the HALT release condition is satisfied.
The system clock operation continues in this mode.
14.3
STANDBY RELEASE CONDITIONS
S-IN input
K
I/O
input
K
I
input
Timer count down operation completion
(1)
(2)
(3)
(4)
Remark
Either high level or low level can be specified for setting a release condition by input.
Table 14-1. Standby Mode Releasing Condition
D
3
0/1
0
Releasing condition:
0
1
Timer
0
1
0
0
K
0
0
S-IN
D
2
D
1
D
0
Releasing
Condition
1
0
1
0
I/O
K
I
Remarks
Released when 0.
Valid only in the IN mode.
When RL A is selected, the standby mode is
always released.
3
“0”···Low level detection
“1”···High level detection
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