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參數(shù)資料
| 型號： | UPD63210LGT |
| 廠商： | NEC Corp. |
| 英文描述： | 16-BIT D/A CONVERTER WITH BUILT-IN DIGITAL FILTER FOR AUDIO |
| 中文描述： | 16位D /一個內(nèi)置轉(zhuǎn)換器，在數(shù)字的音頻過濾器 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 141K |
| 代理商： | UPD63210LGT |
μ
PD63210, 63210L
9
3.2 Data Input Circuit
(1) Input data format
Data on MSB first, 2’s compliment, and backward justification is input.
(2) Selection of input data bit length
An input data bit length is selected by the BSEL (No.14) pin.
Table 3-2. Selection of Input Data Bit Length
(3) Data input timing chart
SDI and LRCKI is incorporated in the internal shift register at the rising edge of BCKI. The SDI, LRCKI, and
BCKI waveforms must satisfy the conditions in the electrical specifications (such as V
IH
, V
IL
under DC
characteristics; and t
BWH
, t
BWL
, t
BW
, t
DS
, t
DH
, t
LRS
, and t
LRH
under AC characteristics).
SDI considers the 16 bits (when BSEL = L; 18 bits when BSEL = H) preceding the change point of LRCKI to be
valid data.
Regarding the combination of system clock selection and input data length selection, the conditions for
inputtable BCKI are shown in Table 3-3.
Table 3-3. Limitations on BCKI
The data input timing charts are shown in Figure 3-3 and Figure 3-4.
Figure 3-3. Data Input Timing Chart (when BSEL = L)
Figure 3-4. Data Input Timing Chart (when BSEL = H)
BSEL
L
H
Input Data Bit Length
16 bits
18 bits
BCKI
32fs
48fs
64fs
16 bits
(BSEL = L)
384fs
(CKSEL = L)
18 bits
(BSEL = H)
-
16 bits
(BSEL = L)
-
18 bits
(BSEL = H)
-
-
512fs
(CKSEL = H)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Lch data
MSB
LSB
Continuous
Invalid
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Rch data
MSB
LSB
Continuous
Invalid
1/fs
BCKI
SDI
LRCKI
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Lch data
MSB
LSB
Continuous
Invalid
Rch data
1/fs
BCKI
SDI
LRCKI
2
1
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
MSB
LSB
Continuous
Invalid
2
1
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