參數(shù)資料
型號(hào): UPD444004LLE-A12
廠商: NEC Corp.
英文描述: 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT
中文描述: 4分位CMOS快速靜態(tài)存儲(chǔ)器100萬(wàn)字的4位
文件頁(yè)數(shù): 7/16頁(yè)
文件大小: 100K
代理商: UPD444004LLE-A12
7
μ
PD444004L
Data Sheet M14427EJ4V0DS
Read Cycle
Parameter
Symbol
-A8
-A10
-A12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
8
10
12
ns
Address access time
t
AA
8
10
12
ns
1
/CS access time
t
ACS
8
10
12
ns
/OE access time
t
OE
4
5
6
ns
Output hold from address change
t
OH
3
3
3
ns
/CS to output in low impedance
t
CLZ
3
3
3
ns
2, 3
/OE to output in low impedance
t
OLZ
0
0
0
ns
/CS to output in high impedance
t
CHZ
4
5
6
ns
/OE to output hold in high impedance
t
OHZ
4
5
6
ns
Notes
1.
See the output load shown in
Figure 1
.
2.
Transition is measured at
±
200 mV from steady-state voltage with the output load shown in
Figure 2
.
3.
These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output)
Previous data out
Data out
Remarks 1.
In read cycle, /WE should be fixed to high level.
2.
/CS = /OE = V
IL
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