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參數(shù)資料
| 型號(hào)： | UPD44165184F5-E60-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 1800萬(wàn)位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 15/32頁(yè) |
| 文件大?。?/td> | 392K |
| 代理商： | UPD44165184F5-E60-EQ1 |
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15
Data Sheet M15825EJ7V
1
DS
μ
PD44165084, 44165184, 44165364
Notes 1.
The device will operate at clock frequencies slower than TKHKH(MAX.).
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once V
DD
and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
±
0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5.
This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1.
This parameter is sampled.
2.
Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3.
Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4.
If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5.
V
DD
Q is 1.5 V DC.
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