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參數(shù)資料
| 型號： | UPD44165084F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT QDRII SRAM 4-WORD BURST OPERATION |
| 中文描述： | 1800萬位推出QDRII SRAM的4個字爆發(fā)運作 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 392K |
| 代理商： | UPD44165084F5-E50-EQ1 |
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17
Data Sheet M15825EJ7V
1
DS
μ
PD44165084, 44165184, 44165364
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
10R
Test Mode Select. This is the command input for the TAP controller state machine.
TDI
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.
TDO
1R
Remark
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (T
A
= 0 to 70°C, V
DD
= 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
JTAG Input leakage current
I
LI
0 V
≤
V
IN
≤
V
DD
–5.0
–
+5.0
μ
A
JTAG I/O leakage current
I
LO
0 V
≤
V
IN
≤
V
DD
Q ,
–5.0
–
+5.0
μ
A
Outputs disabled
JTAG input high voltage
V
IH
1.3
–
V
DD
+ 0.3
V
JTAG input low voltage
V
IL
–0.3
–
+0.5
V
JTAG output high voltage
V
OH1
| I
OHC
| = 100
μ
A
1.6
–
–
V
V
OH2
| I
OHT
| = 2 mA
1.4
–
–
V
JTAG output low voltage
V
OL1
I
OLC
= 100
μ
A
–
–
0.2
V
V
OL2
I
OLT
= 2 mA
–
–
0.4
V
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