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參數(shù)資料
| 型號(hào)： | UPD44164082F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬位的SRAM 2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 282K |
| 代理商： | UPD44164082F5-E50-EQ1 |
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Data Sheet M15821EJ7V2DS
μ
PD44164082, 44164182, 44164362
Burst Sequence
Linear Burst Sequence Table
[
μ
PD44164182,
μ
PD44164362]
A0
A0
External Address
0
1
1st Internal Burst Address
1
0
Truth Table
Operation
/LD
R, /W
CLK
DQ
WRITE cycle
L
L
L
→
H
Data in
Load address, input write data on two
Input data
D(A1)
D(A2)
consecutive K and /K rising edge
Input clock
K(t+1)
↑
/K(t+1)
↑
READ cycle
L
H
L
→
H
Data out
Load address, read data on two
Output data
Q(A1)
Q(A2)
consecutive C and /C rising edge
Output clock
/C(t+1)
↑
C(t+2)
↑
NOP (No operation)
H
X
L
→
H
High-Z
STANDBY(Clock stopped)
X
X
Stopped
Previous state
Remarks 1.
H : High level, L : Low level,
×
: don’t care,
↑
: rising edge.
2.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.
3.
All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4.
This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5.
Refer to state diagram and timing diagrams for clarification.
6.
A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7.
It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44164182F5-E50-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164362F5-E50-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164082F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164182F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324184F5-E50-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44164182AF5-E37Y-EQ2-A | 制造商:Renesas Electronics Corporation 功能描述:UPD44164182A Series 18 Mbit (1 M x 18 ) 270 MHz 0.3 ns DDRII SRAM - BGA-165 |
| UPD44164182F5-E50-EQ1 | 制造商:Renesas Electronics Corporation 功能描述:UPD44164182 Series 18 Mb (1 M x 18 ) 200 MHz 5 ns DDRII SRAM - BGA-165 |
| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
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