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參數(shù)資料
| 型號(hào)： | UPD44164082F5-E50-EQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 1800萬(wàn)位的SRAM 2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 14/32頁(yè) |
| 文件大?。?/td> | 282K |
| 代理商： | UPD44164082F5-E50-EQ1 |
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14
Data Sheet M15821EJ7V2DS
μ
PD44164082, 44164182, 44164362
Read and Write Cycle
Parameter
Symbol
-E40
-E50
-E60
Unit
Note
(250 MHz)
(200 MHz)
(167 MHz)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time (K, /K, C, /C) TKHKH
Clock phase jitter (K, /K, C, /C)
Clock HIGH time (K, /K, C, /C)
Clock LOW time (K, /K, C, /C)
Clock to /clock (K
→
/K., C
→
/C.)
Clock to /clock (/K
→
K., /C
→
C.)
Clock to data clock 200 to 250 MHz
(K
→
C., /K
→
/C.)
167 to 200 MHz
133 to 167 MHz
DLL lock time (K, C)
K static to DLL reset
4.0
8.4
5.0
8.4
6.0
8.4
ns
ns
ns
ns
ns
ns
ns
1
2
3
TKC var
TKHKL
TKLKH
TKH /KH
T /KHKH
TKHCH
TKC lock
TKC reset
–
0.2
–
0.2
–
0.2
1.6
–
2.0
–
2.4
–
1.6
–
2.0
–
2.4
–
1.8
–
2.2
–
2.7
–
1.8
–
2.2
–
2.7
–
0
1.8
–
–
–
–
0
2.3
0
2.3
–
–
0
2.8
0
2.8
0
2.8
< 133 MHz
0
3.55
0
3.55
0
3.55
1,024
–
1,024
–
1,024
–
Cycle
ns
30
–
30
–
30
–
Output Times
C, /C HIGH to output valid
C, /C HIGH to output hold
C, /C HIGH to echo clock valid
C, /C HIGH to echo clock hold
CQ, /CQ HIGH to output valid
CQ, /CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
–
0.45
–
0.45
–
0.5
ns
ns
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–
–0.5
–
–
0.45
–
0.45
–
0.5
–0.45
–
–0.45
–
–0.5
–
–
0.3
–
0.35
–
0.4
4
4
–0.3
–
–0.35
–
–0.4
–
–
0.45
–
0.45
–
0.5
–0.45
–
–0.45
–
–0.5
–
Setup Times
Address valid to K rising edge
Synchronous load input (/LD),
read write input (R, /W) valid to
K rising edge
Data inputs and write data select
inputs (/BWx, /NWx) valid to
K, /K rising edge
TAVKH
TIVKH
TDVKH
0.5
–
0.6
–
0.7
–
ns
ns
ns
5
5
5
0.5
–
0.6
–
0.7
–
0.35
–
0.4
–
0.5
–
Hold Times
K rising edge to address hold
K rising edge to
synchronous load input (/LD),
read write input (R, /W) hold
K, /K rising edge to data inputs and
write data select inputs (/BWx, /NWx)
hold
TKHAX
TKHIX
TKHDX
0.5
–
0.6
–
0.7
–
ns
ns
ns
5
5
5
0.5
–
0.6
–
0.7
–
0.35
–
0.4
–
0.5
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44164182F5-E50-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164362F5-E50-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164082F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44164182F5-E60-EQ1 | 18M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| UPD44324184F5-E50-EQ2 | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44164182AF5-E37Y-EQ2-A | 制造商:Renesas Electronics Corporation 功能描述:UPD44164182A Series 18 Mbit (1 M x 18 ) 270 MHz 0.3 ns DDRII SRAM - BGA-165 |
| UPD44164182F5-E50-EQ1 | 制造商:Renesas Electronics Corporation 功能描述:UPD44164182 Series 18 Mb (1 M x 18 ) 200 MHz 5 ns DDRII SRAM - BGA-165 |
| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
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