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參數(shù)資料
| 型號(hào)： | UPD4416001G5-A17-9JF |
| 廠商： | NEC Corp. |
| 英文描述： | 16M-BIT CMOS FAST SRAM 16M-WORD BY 1-BIT |
| 中文描述： | 1,600位CMOS快速靜態(tài)存儲(chǔ)器1,600 - Word的1位 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大小： | 83K |
| 代理商： | UPD4416001G5-A17-9JF |
Data Sheet M14077EJ3V0DS
6
μ
PD4416001
Read Cycle
Parameter
Symbol
-A15
-A17
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
15
17
ns
Address access time
t
AA
15
17
ns
1
/CS access time
t
ACS
15
17
ns
/OE access time
t
OE
7
8
ns
Output hold from address change
t
OH
3
3
ns
/CS to output in low impedance
t
CLZ
3
3
ns
2, 3
/OE to output in low impedance
t
OLZ
0
0
ns
/CS to output in high impedance
t
CHZ
7
8
ns
/OE to output hold in high impedance
t
OHZ
7
8
ns
Notes
1.
See the output load shown in
Figure 1
.
2.
Transition is measured at
±
200 mV from steady-state voltage with the output load shown in
Figure 2
.
3.
These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
D
OUT
(Output)
Previous data output
Data output
Remarks 1.
In read cycle, /WE should be fixed to high level.
2.
/CS = /OE = V
IL
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
t
RC
t
AA
t
OLZ
/CS (Input)
Data output
t
OHZ
High impedance
t
ACS
/OE (Input)
t
OE
t
CLZ
t
CHZ
High impedance
D
OUT
(Output)
Caution
Address valid prior to or coincident with /CS low level input.
Remark
In read cycle, /WE should be fixed to high level.
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