參數(shù)資料
型號： UPD31172F1-48-FN
元件分類： 外設及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA208
封裝： 15 X 15 MM, PLASTIC, FBGA-208
文件頁數(shù)： 21/44頁
文件大?。?/td> 279K
代理商： UPD31172F1-48-FN
Data Sheet U14388EJ2V0DS00
28
PD31172
(a)
Serial BAUDOUT timing
tBHD
tBLD
tBHD
tBLD
CLK
(internal, 1.8462 MHz)
BAUDOUTB
(1 cycle) (internal)
BAUDOUTB
(2 cycles) (internal)
BAUDOUTB
(3 cycles) (internal)
BAUDOUTB
(N cycles, N > 3)
(internal)
tBHD
tHW
tLW
tHW
tLW
(b)
Serial receive timing
RCLK
(BAUDOUTB)
Internal sample clock
RXD (input)
Internal sample clock
INTRP (output)
(receive data existence interrupt
Note 1)
INTRP (output)
(receive status interrupt
Note 2)
IOR# (input)
(reading RBR register)
IOR# (input)
(reading LSR register)
tSINT
tRINT2
tSCD
8 RCLKC
Start bit
Stop bit
Parity bit
DATA (5:8)
16 RCLKC
tRINT1
Notes 1. Dependant on the existence of receive data. At this time, bit 0 of the IER register is 1, and bits 3 to
1 of the IIR register are 0, 1, 0, respectively.
2. Dependant on the receive line status. At this time, bit 2 of the IER register is 1, and bits 3 to 1 of the
IIR register are 0, 1, 1, respectively.
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