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參數(shù)資料
| 型號： | UPD2845GR-E2 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E2 |
8
P
PD2845GR
INPUT TIMING OF SERIAL DATA
latch
DATA
CLK
LE
read
This logic circuit is controlled by a 3-wire serial bus interface with DATA (12 pin), CLK (13 pin) and LE (14 pin).
On the control setting, Binary-coded serial data is input to DATA pin. This data is read into the shift register at the
rising edge of the CLK signal input to the CLK pin. When the LE signal is at the low level, DATA CLK are received
into the LSI to be latched at the rising edge of the LE signal.
While the LE signal is at the high level, neither DATA nor CLK signals can be received.
CAUTION At the initial V
CC
supplied time, serial data must be input, because the IC output is unstable on
the non-data input stage. [Refer to ‘Power-save (pin 11)’ on 12 page]
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