參數(shù)資料
型號： UPD178F054
英文描述： 78K/0 Series for Instructions | User＇s Manual[10/2001]
中文描述： 78K線/ 0系列說明|用戶手冊[10/2001]
文件頁數(shù)： 37/129頁
文件大?。?/td> 644K
代理商： UPD178F054
15
CHAPTER 2 REGISTERS
User's Manual U12326EJ4V0UM
(1) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgement operations of the CPU.
When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts
are all disabled.
When IE = 1, the IE flag is set to interrupt enable (EI), and interrupt request acknowledgement is controlled
by an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
This flag is reset (0) upon DI instruction execution or interrupt request acknowledgment and is set (1) upon
execution of the EI instruction.
(2) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(3) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags used to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SBL RBn instruction
execution is stored.
(4) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(5) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, vectored
interrupt requests specified as low priority by the priority specification flag register (PR) are disabled for
acknowledgment. Actual acknowledgment for interrupt requests is controlled by the state of the interrupt
enable flag (IE).
(6) Carry flag (CY)
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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PDF描述
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