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參數(shù)資料
| 型號： | UPD17242UC-XXX-5A4 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.5 MHz, MICROCONTROLLER, PDSO30 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-30 |
| 文件頁數(shù)： | 63/102頁 |
| 文件大?。?/td> | 953K |
| 代理商： | UPD17242UC-XXX-5A4 |
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63
Data Sheet U15002EJ1V1DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.2
Hardware of Interrupt Controller
This section describes the flags of the interrupt controller.
(1)
Interrupt request flag and interrupt enable flag
The interrupt request flag (IRQ
×××) is set to 1 when an interrupt request is generated, and is automatically
cleared to 0 when the interrupt processing is executed.
An interrupt enable flag (IP
×××) is provided for each interrupt request flag. When the IP××× flag is 1, the
interrupt is enabled; when it is 0, the interrupt is disabled.
(2)
EI/DI instruction
Whether an acknowledged interrupt is executed or not is specified by the EI or DI instruction.
When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The
INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by
an instruction.
The DI flag clears the INTE flag to 0 to disable all the interrupts.
The INTE flag is also cleared to 0 at reset, disabling all the interrupts.
Table 8-2. Interrupt Request Flags and Interrupt Enable Flag
Interrupt
Signal Setting Interrupt Request Flag
Interrupt
Request Flag
Enable Flag
IRQTM
Reset by 8-bit timer.
IPTM
IRQ
Set when edge of INT pin input signal is detected
IP
IRQBTM
Reset by basic interval timer.
IPBTM
8.2.1
INT
This flag reads the INT pin status.
When a high level is input to the INT pin, this flag is set to 1; when a low level is input, the flag is reset to 0.
32
10
00
0
INT
Address
RF: 0FH
INT
After reset
Undefined
R/W
R
0
1
INT pin level detection
INT pin: Low level
INT pin: High level
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