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參數(shù)資料
| 型號(hào)： | UPD16879 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 199K |
| 代理商： | UPD16879 |
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Data Sheet S14188EJ1V0DS00
27
μ
PD16879
Initialization
The IC operation can be initialized as follows:
(1) Turns ON V
DD
.
(2) Make RESET input low level signal.
In initial mode, the operating status of the IC is as shown in Table 18.
Table 18. Operations in Initial Mode
Item
Specification
Current consumption
100
μ
A
OSC
Input of external clock is inhibited.
V
D
, V
D
Input inhibited.
FF1 to FF7
Low level
Pulse out
Low level
EXP0, EXP1
Low level in the case of (1) above.
Previous value is retained in the case of (2) above.
Serial operation
Can be accessed after initialization in the case of (1) above.
Can be accessed after RESET has gone high level in the case of (2) above.
Step pulse output is inhibited and FF7 is made low level if the following conditions are satisfied.
(1) If the set number of pulses (6th/10th byte) is “0”.
(2) If the checksum value is other than “0”.
(3) If the first point wait time (FF1) is set to 1V
D
or longer.
(4) If the first point wait time + first point magnetize wait time (FF2) is set to 1V
D
or longer.
(5) If the first point wait time (FF1) is completed earlier than falling timing of LATCH.
(6) If V
D
is not input.
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