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參數(shù)資料
| 型號： | UPD16879 |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 199K |
| 代理商： | UPD16879 |
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Data Sheet S14188EJ1V0DS00
25
μ
PD16879
About Power Save Mode
It is possible that circuit electric current is made small in the power saving (the following PS) mode.
Data maintenance just before the PS mode and the maintenance of the phase position are done in the PS mode.
Circuit consumption current in the PS mode becomes 300
μ
A (MAX.) at the time of the outside clock (OSC
IN
) = 4.5
MHz, and becomes 100
μ
A (MAX.) at the time of the outside clock (OSC
IN
) stopped. It can be reduced in less than
1/10 in normal mode.
(How to be within PS mode)
The establishment of the PS mode is done by a D7 bits of the 4th byte.
Please follow the following process when it is within PS mode.
(1)
Normal operation (Pulse number > 1, enable: conducts)
↓
(2-1) Normal operation (Pulse number = 0, enable: conducts)
(2-2) Normal operation (Pulse number = 0, enable: stops)
↓
(3)
Please input PS data.
(Effective timing of PS mode)
Chopping movement stops at the LATCH falling timing which PS data are contained to.
First point wait count and first point magnetize wait count stop at the next V
D
rising timing which PS data are
contained to. FF1 is fixed on the high level, and FF2 is fixed on low level.
Enable becomes low level at the LATCH falling timing which PS data are contained to.
And, the outside expansion circuit (EXP terminal) works at the time of PS mode too.
(PS mode release movement)
Chopping movement resumes at the LATCH falling timing which PS release data are contained to.
First point wait count and first point magnetize wait count resume at the next V
D
rising timing which PS release
data are contained to.
Enalbe becomes high level at the first FF1 falling timing which PS release data are contained to. (When enable
data is high level)
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