![](http://datasheet.mmic.net.cn/370000/UPD16772A_datasheet_16743675/UPD16772A_7.png)
Data Sheet S14725EJ1V0DS00
7
μ
PD16772A
Figure 5–2. Relationship between Input Data and Output Voltage
V
DD2
– 0.2 V > V
0
> V
1
> V
2
> V
3
> V
4
> 0.5 V
DD2
, POL21/22 = L
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
rn
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r total
(
)
1150
700
700
700
700
350
350
350
350
350
350
350
350
300
300
300
200
200
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
150
150
150
150
150
250
250
250
300
300
300
450
1100
15850
V0'
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
V63'
V0
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1+(V0-V1)×
V1
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4
6500 /
5800 /
5100 /
4400 /
3700 /
3350 /
3000 /
2650 /
2300 /
1950 /
1600 /
1250 /
900 /
600 /
300 /
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
2100 /
1900 /
1700 /
1500 /
1300 /
1150 /
1000 /
850 /
700 /
600 /
500 /
400 /
300 /
200 /
100 /
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
1550 /
1450 /
1350 /
1250 /
1150 /
1050 /
950 /
850 /
750 /
650 /
550 /
450 /
350 /
250 /
150 /
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
4100 /
3950 /
3800 /
3650 /
3500 /
3350 /
3200 /
2950 /
2700 /
2450 /
2150 /
1850 /
1550 /
1100 /
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
Output votage
Caution
There is no connection between V
4
and V
5
terminal in the chip.
V
0
'
V
17
'
V
1
'
V
47
'
V
2
'
V
48
'
V
3
'
V
49
'
V
15
'
V
16
'
V
63
'
V
61
'
V
62
'
r0
r17
r1
r47
r46
r2
r48
r3
r49
r14
r15
r16
r60
r61
r62
V
4
V
3
V
1
V
0