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參數(shù)資料
| 型號(hào)： | UPD16682P |
| 廠商： | NEC Corp. |
| 英文描述： | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 1 / 65稅LCD控制器/驅(qū)動(dòng)器，片內(nèi)RAM |
| 文件頁數(shù)： | 8/56頁 |
| 文件大?。?/td> | 435K |
| 代理商： | UPD16682P |
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Data Sheet S13368EJ3V0DS00
8
μ
PD16682
3.2 Logic System Pins (1/2)
Pin Symbol
Pin Name
Pad No.
I/O
Function Description
P,/S
Select data input
79
Input
This pin is used to select between parallel data input and serial
data input.
P,/S = H : Parallel data input
P,/S = L : Serial data input
This setting cannot be switched after power-on. For details, see
5. DESCRIPTION OF FUNCTIONS
.
/CS1,CS2
Chip select
8,9
Input
These pins are used for the chip select signal. When /CS1 = L
and CS2 = H, this signal is active and can be used for I/O of data
and commands.
/RD(E)
Read (enable)
15
Input
When connected to 80 series MPU : active low
This pin connects the 80 series MPU’s RD signal. Data bus
output status is set when this signal is low.
When connected to 68 series MPU : active high
It is used as the enable clock input pin for the 68 series MPU.
/WR(R,/W)
Write (read/write)
14
Input
When connected to 80 series MPU: active low
This pin connects the 80 series MPU's /WR signal. Signals on
the data bus are latched at the rising edge of the /WR signal.
When connected to 68 series MPU
This pin is an input pin for read/write control signals.
R,/W = H : Read
R,/W = L : Write
C86
Interface select
78
Input
This pin is used to select the MPU interface.
C86 = H : 68 series MPU interface
C86 = L : 80 series MPU interface
D
0
to D
5
Data bus
17 to 22
Input
/Output
When used with a parallel interface, these pins correspond to
data bus bits D
0
to D
5
.
When used with a serial interface, they are pulled down
internally.
D
6
(SCL)
Data bus/serial clock
23
Input
/Output
When used with a parallel interface, this pin corresponds to data
bus bit D
6
.
When used with a serial interface, it is a serial clock input pin.
D
7
(SI)
Data bus/serial data input
24
Input
/Output
When used with a parallel interface, this pin corresponds to data
bus bit D
7
.
When used with a serial interface, it is a serial data input pin.
A0
Data command
12
Input
This pin is connected to the LSB in the ordinary MPU address
bus to distinguish between data and commands.
A0 = H : Indicates that display data exists in bits D
0
to D
7
.
A0 = L : Indicates that display control commands exist in bits D
0
to D
7
.
TEST
OUT
Test output
6
Output This pin is used as a test output. Leave this pin open when used
for this purpose.
/RES
Reset
11
Input
This pin is used to perform an internal reset when at low level.
CLK
Clock select
76
Input
This pin is used to select the valid/invalid setting for the display
clock’s on-chip oscillation circuit.
CLS = H : On-chip oscillation circuit is valid
CLS = L : On-chip oscillation circuit is invalid (external input)
When CLS = L, a display clock is input via the CL pin.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD16682P-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-002 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-004 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682W | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
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