參數(shù)資料
型號： UPD16682P
廠商： NEC Corp.
英文描述： 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
中文描述： 1 / 65稅LCD控制器/驅(qū)動器，片內(nèi)RAM
文件頁數(shù)： 14/56頁
文件大?。?/td> 435K
代理商： UPD16682P
Data Sheet S13368EJ3V0DS00
14
μ
PD16682
5.1.3 Serial interface
If the serial interface has been selected (P,/S = L) and if the chip is in the active state (/CS1 = L and CS2 = H), both
serial data input (SI) and serial clock input (SCL) can be received. The serial interface includes an 8-bit shift register
and a 3-bit counter. Serial data is captured at the rising edge of the serial clock and is clocked in via the serial data
input pins in sequence from D
7
to D
0
. At the rising edge of the eighth serial clock, data is converted to 8-bit parallel
data.
Input via the A0 pin can be used to determine whether the input serial data is display data or a command (display
data when A0 = H, command when A0 = L). The timing for reading and identifying input via A0 occurs at the rising
edge of the “eighth x n” serial clock once the chip’s status is active.
A serial interface signal chart is shown below.
Figure 5
3. Serial Interface chart
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
/CS1
SI
SCL
A0
CS2
Remarks1.
When the chip’s status is inactive, the shift register and counter are both reset to their initial values.
2.
Data cannot be read when using the serial interface.
3.
For the SCL signal, caution is advised concerning the wire’s terminating reflection and noise from
external sources. We recommend to check the operation on the actual equipment.
5.1.4 Chip select
The
μ
PD16682 has two chip select pins (/CS1 and CS2). The MPU interface or serial interface can be used only
when /CS1 = L and CS2 = H.
When the chip select pin is inactive, D
7
to D
0
are set to high impedance (invalid) and input of A0, /RD, or /WR is
invalid. If the serial interface has been selected, the shift register and counter are both reset.
5.1.5 Display data RAM and internal register access
Access to the
μ
PD16682 from the MPU supports high-speed data transfers since the cycle time (t
CYC
) is met and
there is no need for wait time.
When data transfer occurs between the
μ
PD16682 and the MPU, the data is held in a bus holder belonging to the
internal data bus and is written to the display data RAM before the next data write cycle. When the MPU reads the
contents of the display data RAM, the data read during the first data read cycle (dummy cycle) is first held in the bus
holder and is read from the bus holder to the system bus during the next data read cycle.
Note with caution that, due to constraints on the read sequence for the display data RAM, when the address is set,
the data is not output from the address specified by the next read command but rather is output to the address
specified during the second data read operation. Consequently, one dummy read operation is strictly required after
setting an address or after a write cycle. Figure 5
4 illustrates this situation.
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