參數(shù)資料
型號: UPD16682N
廠商: NEC Corp.
英文描述: 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
中文描述: 1 / 65稅LCD控制器/驅(qū)動器,片內(nèi)RAM
文件頁數(shù): 11/56頁
文件大?。?/td> 435K
代理商: UPD16682N
Data Sheet S13368EJ3V0DS00
11
μ
PD16682
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in the following
table.
Pin Name
I/O
Recommended Connection of Unused Pins
Notes
P,/S
Input
Mode setting pin
1
/CS1
Input
Connect to V
SS
CS2
Input
Connect to V
DD
/RD(E)
Input
Connect to V
DD
(80 series interface),
connect to V
DD
or V
SS
(serial interface)
/WR (R,/W)
Input
Connect to V
DD
or V
SS
(serial interface)
C86
Input
Mode setting pin
1
D
0
to D
5
Input/Output
Leave open (when using serial interface)
4
D
6
(SCL)
Input/Output
D
7
(SI)
Input/Output
A0
Input
Data/command setting pin
2
TEST
OUT
Output
Leave open
/RES
Input
Connect to V
DD
CLS
Input
Mode setting pin
1
FR
Input/Output
Leave open (when using master mode, M,/S = H)
FRS
Output
Leave open
/DOF
Input/Output
Leave open (when using master mode, M,/S = H)
M,/S
Input
Mode setting pin
1
CL
Input/Output
Display clock
3
HPM
Input
Mode setting pin
1
IRS
Input
Mode setting pin
1
TEST1
Input
Leave open
4
TEST2
Input
Leave open
4
TEST3
Input
Leave open
4
TEST4
Output
Leave open
TEST5
Output
Leave open
Notes 1.
Connect to V
DD
or V
SS
according to the selected mode.
2.
Input microcontroller output from V
DD
or V
SS
according to the selected register.
3.
This pin is an output when M,/S = H and CLS = H but should otherwise be used to input the display clock.
4.
These pins are pulled down to V
SS
in the IC.
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