![](http://datasheet.mmic.net.cn/370000/UPD16448A_datasheet_16740553/UPD16448A_4.png)
4
μ
PD16448A
1. PIN DESCRIPTION
Symbol
Name
Function
C
1
to C
3
Video signal input
Input R, G, and B video signals.
H
1
to H
240
Video signal output
Video signal output pins. Output sampled and held video signals during
horizontal period.
STHR
STHL
Cascade I/O
Start pulse I/O pins of sample hold timing. STHR serves as an input pin
and STHL, as an output pin, in the case of right shift. In the case of left
shift, STHL serves as an input pin, and STHR, as an output pin.
CLI
1
CLI
2
CLI
3
Shift clock input
A start pulse is read at the rising edge of CLI
1
. Sampling pulse SHP
n
is
generated at the rising edge of CLI
1
through CLI
3
during successive
sampling, and at the rising edge of CLI
1
during simultaneous sampling
(for details, refer to the
Timing charts
in
2.FUNCTION DESCRIPTION
).
INH
Inhibit input
Selects a multiplexer and one of the two sample and hold circuits at the
falling edge.
RESET
Reset input
Resets the select counter of the multiplexer and the selector circuit of
the two sample and hold circuits when it goes high. After reset, the
multiplexer is turned OFF, so sure to input one pulse of the INH signal
before inputting the video signal. If the video signal is input without the
INH signal, sampling is not executed.
Four types of color filter arrays can be supported by combination of
MP/TH and MP/1.5.
Mode
MP/TH
MP/1.5
MP/TH
Multiplexer circuit select input (1)
Vertical stripe array
L
L
Single-side delta array
L
H
Mosaic array
H
L
Double-side delta array
H
H
MP/1.5
Multiplexer circuit select input (2)
R/L
Shift direction select input
R/L = H; right shift: STHR
→
H
1
→
H
240
→
STHL
R/L = L; left shift: STHL
→
H
240
→
H
1
→
STHR
V
DD1
Logic power supply
3.0 V to 5.5 V
V
DD2
Driver power supply
5.0 V
±
0.5 V
V
SS1
Logic ground
Connect this pin to ground of system.
V
SS2
Driver ground
Connect this pin to ground of system.
V
SS3
Driver ground
Connect this pin to ground of system.
TEST
Test pin
Fix this pin to L.