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參數(shù)資料
| 型號： | UPD16448AN |
| 廠商： | NEC Corp. |
| 英文描述： | SOURCE DRIVER FOR 240-OUTPUT TFT-LCD NAVIGATION, AUTOMOBILE LCD-TV |
| 中文描述： | 240源驅(qū)動器輸出的TFT - LCD導(dǎo)航，汽車液晶電視 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 133K |
| 代理商： | UPD16448AN |
19
μ
PD16448A
SWITCHING CHARACTERISTICS (T
A
= -30 to +85
°
C, V
DD1
= 3.0 to 5.5 V, V
DD2
= 5.0
±
0.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
t
PHL
C
L
= 20 pF
10
54
ns
Start pulse propagation delay time
t
PLH
C
L
= 20 pF
10
54
ns
Maximum clock frequency 1
f
max. 1
15
MHz
Maximum clock frequency 2
f
max. 2
With 3-phase clock input
8
MHz
Logic input capacitance
C
I1
Other than STHL, STHR
15
pF
STHL, STHR input capacitance
C
I2
STHL, STHR
20
pF
Video input capacitance
C
3
C
1
to C
3
, V
VI
= 2.0 V
50
pF
TIMING REQUIREMENTS (T
A
= -30 to +85
°
C, V
DD1
= 3.0 to 5.5 V, V
DD2
= 5.0
±
0.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock pulse width
PW
CLI
Duty = 50 %
33
ns
Start pulse setup time
t
SETUP
8
ns
Start pulse hold time
t
HOLD
8
ns
Reset pulse width
PW
RES
66
ns
INH setup time
t
ISETUP
33
ns
INH hold time
t
IHOLD
33
ns
Reset-INH time
t
R-I
81
ns
INH pulse width
PW
INH
5
CLK
Remark
Keep the rise and fall times of the logic input signals to within t
r
= t
f
= 5 ns (10 to 90%).
As an example, the switching characteristic wave of CLI
1
is defined on the next page.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16449 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16449 Data Sheet | Data Sheet[05/2002] |
| UPD16449N | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16449N-XXX | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16449P | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16454A | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT |
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