參數(shù)資料
型號: UPC1857ACT
廠商: NEC Corp.
英文描述: SOUND CONTROL IC WITH SURROUND AND I2C BUS
中文描述: 聲控集成電路環(huán)繞和I2C總線
文件頁數(shù): 24/44頁
文件大?。?/td> 343K
代理商: UPC1857ACT
24
μ
PC1857A
4.4.6
Automatic increment
The automatic increment function can be turned ON/OFF by using the data of bit D6 of subaddresses 01H through
04H.
This is effective when transmitting data successively (refer to
3.2.2 Successive data transfer
).
Figure 4-6. Automatic Increment
D7
D6
D5
D4
D3
D2
D1
D0
Subaddress
01H-04H
Don't care
Automatic
increment
Don't care
0
1
Automatic increment: OFF
Automatic increment: ON
Automatic increment
Caution Subaddress 00H does not have an automatic increment function. It is always set to ON.
The automatic increment function automatically increments the subaddress when data is transferred successively.
Automatic increment ON : The subaddress is automatically incremented immediately after byte data with D6 = 1
has been transferred.
This setting is useful if the data at every subaddress is to be set at once for
initialization. The subaddress is always incremented immediately after the data of
subaddress: 00H has been transferred.
Automatic increment OFF : The subaddress is fixed immediately after byte data with D6 = 0 has been
transferred. This setting is useful when the data at the same subaddress is to be
successively changed, for example to turn up/down the volume.
There is an automatic increment function ON/OFF bit in subaddresses 01H through 04H. Incrementing
subaddresses is individually controlled by the automatic increment function ON/OFF bit of each subaddress.
For example, if the automatic increment function of subaddress 01H is turned ON, and that of subaddress 02H is
turned OFF, the subaddress is automatically incremented from 01H to 02H, and is fixed to 02H.
Even if the automatic increment function ON/OFF bit of subaddress 04H is set to ON, the subaddress is not
incremented. If the next data is transferred after the data of 04H has been set (acknowledge bit: L), acknowledge
enters the NAK status (acknowledge bit: H), and data transfer from the host CPU is stopped.
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