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參數(shù)資料
| 型號(hào)： | UPC1854A |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿(mào)易體制處理LSI |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 251K |
| 代理商： | UPC1854A |
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μ
PC1854A
15
Data Sheet S12816EJ3V0DS00
2.2 SAP Demodulation Block
(1) SAP BPF
Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 f
H
. The filter response is
adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(2) Noise BPF
The
μ
PC1854A monitors signals picked up by the noise band-pass filter (f
O
180 kHz), and distinguishes noise
from signals. By this method, the
μ
PC1854A prevents faulty SAP detection in a weak electric field. The filter
response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(3) Noise detector
Performs full-wave rectification of noise from noise band-pass filter, changes it to the DC voltage, and inputs it
to the comparator. When the noise level exceeds the reference level, the detector recognizes noise, and the
noise detection bit (read register, bit D4) is set “1”.
The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor
connected to the NDT.
(4) SAP detector
Detects the signal from the SAP band-pass filter and smooths it through the SDT pin and inputs it to the
comparator. When the SAP signal is detected, the SAP signal bit (read register, bit D5) is set “1”.
(5) SAP demodulation circuit
The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit).
The SAP VCO oscillates at 10 f
H
, and performs phase comparison between the signal divided by 2 of the VCO
frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the
SAP VCO setting bits (write register, subaddress 05H, bits D0 to D5).
(6) SAP LPF
Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order low-pass filter and f
H
trap filter. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits
D0 to D5).
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