參數(shù)資料
型號(hào)： UDA1380HN/N2,118
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Stereo audio coder-decoder for MD, CD and MP3; Package: SOT617-1 (HVQFN32); Container: Reel Pack, SMD, 13"
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù)： 33/68頁(yè)
文件大?。?/td> 349K
代理商： UDA1380HN/N2,118
2004 Apr 22
39
Philips Semiconductors
Product specication
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.8
Mode, bass boost and treble
Table 38 Register address 12H
Table 39 Description of register bits
Table 40 Flat/minimum/maximum setting bits
11100100
∞
:::::::::
11111100
∞
BIT
15
14
13
12
11
10
9
8
Symbol
M1
M0
TRL1
TRL0
BBL3
BBL2
BBL1
BBL0
Default
0
BIT
76543210
Symbol
TRR1
TRR0
BBR3
BBR2
BBR1
BBR0
Default
0
BIT
SYMBOL
DESCRIPTION
15 and 14
M[1:0]
Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound
processing lters of bass boost and treble. Default value 00, see Table 40.
13 and 12
TRL[1:0]
Treble setting left. A 2-bit value to program the mode of the sound processing lter of
treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41.
11 to 8
BBL[3:0]
Bass boost setting left. A 4-bit value to program the bass boost setting, which can be set
for left and right independently. The used set depends on the bits M1 and M0. Default
value 0000, see Table 42.
7 and 6
default value 00
5 and 4
TRR[1:0]
Treble setting right. A 2-bit value to program the mode of the sound processing lter of
treble. Default value 00, see Table 41.
3 to 0
BBR[3:0]
Bass boost setting right. A 4-bit value to program the bass boost setting, which can be
set for left and right independently. The used set depends on the mode bits. Default
value 0000, see Table 42.
M1
M0
Mode
0
at (default)
0
1
minimum
1
0
minimum
1
maximum
VC2_7
VC1_7
VC2_6
VC1_6
VC2_5
VC1_5
VC2_4
VC1_4
VC2_3
VC1_3
VC2_2
VC1_2
VC2_1
VC1_1
VC2_0
VC1_0
VOLUME
(dB)
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參數(shù)描述
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