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參數(shù)資料
| 型號(hào)： | UDA1380HN/N2,118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3; Package: SOT617-1 (HVQFN32); Container: Reel Pack, SMD, 13" |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32 |
| 文件頁(yè)數(shù)： | 10/68頁(yè) |
| 文件大?。?/td> | 349K |
| 代理商： | UDA1380HN/N2,118 |
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2004 Apr 22
18
Philips Semiconductors
Product specication
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8.9
Application modes
The operation mode can be set with pin SEL_L3_IIC,
either to L3-bus mode (LOW) or to the I2C-bus mode
(HIGH) as given in Table 5.
For all features in microcontroller mode see Chapter 9.
Table 5
Pin function in the selected mode
Remark: In the I2C-bus mode there is a bit A1 which sets
the LSB bit of the address of the UDA1380. In
L3-bus mode this bit is not available, meaning the device
has only one L3-bus device address.
8.10
Power-on reset
The UDA1380 has a dedicated reset pin, which has a
pull-down resistor. This way a Power-on reset circuit can
be made with a capacitor and a resistor at the pin. The
internal pull-down resistor cannot be used because of the
5 V tolerant nature of the pad. The pull-down resistor is
shielded from the outside world by a transmission gate in
order to support 5 V tolerance.
The reset timing is determined by the external capacitor
and resistor which are connected to pin RESET, and the
internal pull-down resistor. On Power-on reset, all the
digital sound processing features and the system
controlling features are set to the default setting of the
L3-bus and I2C-bus control modes.
Remark: The reset time should be at least 1
s, and
during the reset time the system clock should be running.
In case the WSPLL is selected as the clock source, a clock
must be connected to the SYSCLK input in order to have
a proper reset of the L3-bus or I2C-bus registers. This is
because the clock source is set to SYSCLK by default.
8.11
Power-down requirements
The following blocks have power-down control via the
L3-bus or I2C-bus interface:
Microphone amplifier (LNA) including its Single-Ended
to Differential Converter (SDC) and VGA
ADC plus SDC and the PGA, for left and right separate
Bias generation circuit for the front-end and the FSDAC
Headphone driver
WSPLL
FSDAC.
Clocks of the decimator, interpolator and the analog blocks
have separate enable and disable controls.
PIN
L3-BUS MODE
SEL_L3_IIC = L
I2C-BUS MODE
SEL_L3_IIC = H
L3CLOCK/SCL
L3CLOCK
SCL
L3MODE
A1
L3DATA/SDA
L3DATA
SDA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UDA1380HN-T | 功能描述:接口—CODEC STEREO AUDIO CODER-DECODER RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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