參數(shù)資料
型號： UDA1351TS
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： 96 kHz IEC 958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： PLASTIC, SSOP-28
文件頁數(shù)： 26/36頁
文件大?。?/td> 157K
代理商： UDA1351TS
2000 Feb 18
26
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
Notes
1.
2.
All supply pins V
DD
and V
SS
must be connected to the same external power supply unit.
When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100
must be used in
order to prevent oscillations in the output stage of the operational amplifier.
The output voltage of the DAC is proportional to the DAC power supply voltage.
3.
12 TIMING CHARACTERISTICS
V
DDD
= V
DDA
= 2.7 to 3.6 V; T
amb
=
40 to +85
°
C; R
L
= 5 k
; all voltages measured with respect to ground; unless
otherwise specified.
(THD + N)/S total harmonic
distortion-plus-noise to signal
ratio
f
i
= 1.0 kHz tone at 48 kHz
at 0 dB
at
40 dB; A-weighted
f
i
= 1.0 kHz tone at 96 kHz
at 0 dB
at
40 dB; A-weighted
f
i
= 1.0 kHz tone; code = 0;
A-weighted
f
i
= 1.0 kHz tone; code = 0;
A-weighted
f
i
= 1.0 kHz tone
f
i
= 1.0 kHz tone
90
60
85
55
dB
dB
95
85
58
100
80
53
dB
dB
dB
S/N
signal-to-noise ratio at 48 kHz
signal-to-noise ratio at 96 kHz
95
100
dB
α
cs
V
o
IEC 958 inputs
channel separation
unbalance of output voltages
0.4
96
0.1
dB
dB
V
i(p-p)
AC input voltage
(peak-to-peak value)
input resistance
hysteresis voltage
0.2
0.5
3.3
V
R
i
V
hys
6
40
k
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Device reset
t
rst
PLL lock time
reset active time
250
μ
s
t
lock
time to lock
f
s
= 32.0 kHz
f
s
= 44.1 kHz
f
s
= 48.0 kHz
f
s
= 96.0 kHz
85.0
63.0
60.0
40.0
ms
ms
ms
ms
I
2
S-bus timing
(see Fig.8)
T
cy(BCK)
bit clock cycle time
T
s
= cycle time of sample
frequency
1
64
T
s
s
t
BCKH
t
BCKL
t
r
bit clock HIGH time
bit clock LOW time
rise time
140
140
280
280
20
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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