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參數(shù)資料
| 型號： | UDA1351TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 96 kHz IEC 958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 157K |
| 代理商： | UDA1351TS |
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2000 Feb 18
10
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
8.2
Clock regeneration and lock detection
The UDA1351H contains an on-board PLL for
regenerating a system clock from the IEC 958 input
bitstream or the incoming digital data stream via the data
input interface. In addition to the system clock for the
on-board digital sound processing the PLL also generates
a 256f
s
clock output for use in the application. In the
absence of an input signal the clock will generate a
minimum frequency to warrant system functionality.
Note
: in case of no input signal, the PLL generates a
minimum frequency and the output spectrum shifts
accordingly. Since the analog output does not have a
analog mute, this means noise which is out of band noise
under normal operation conditions, can move into the
audio band.
When the on-board clock has locked to the incoming
frequency the lock indicator bit will be set and can be read
via the L3 interface. Internally the PLL lock indication is
combined with the PCM status bit of the input data stream.
When both the IEC 958 decoder and the on-board clock
have locked to the incoming signal and the input data
stream is PCM data, then pin LOCK will be asserted.
However, when the IC is locked but the PCM status bit
reports non-PCM data then pin LOCK is returned to LOW
level.
The lock indication output can be used, for example, for
muting purposes. The lock signal can be used to drive an
external analog muting circuit to prevent out of band noise
to become audible in case the PLL runs at its minimum
frequency (e.g. when there is no SPDIF input signal).
8.3
Mute
The UDA1351H is equipped with a cosine roll-off mute in
the DSP data path of the DAC part. Muting the DAC, by
pin MUTE (in static mode) or via bit MT (in L3 mode) will
result in a soft mute as presented in Fig.3. The cosine
roll-off soft mute takes 32
×
32 samples = 24 ms at a
sampling frequency of 44.1 kHz.
When operating in the L3 control mode the device will
mute on start-up. In L3 mode it is necessary to explicitly
switch off the mute for audio output by means of the MT bit
in the L3 register.
In the L3 mode pin MUTE does not have any function (the
same holds for several other pins) and can either be left
open-circuit (since it has an internal pull-down resistor) or
be connected to ground.
handbook, halfpage
mute
factor
0
1
3
0
0.8
MGS755
2
0.6
0.4
0.2
t (ms)
Fig.3 Mute as a function of raised cosine roll-off.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UDA1351TS/N1,512 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 96KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| UDA1351TS/N1,518 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 96KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| UDA1351TSDB | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 96KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| UDA1352HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:48 kHz IEC 60958 audio DAC |
| UDA1352TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:48 kHz IEC 60958 audio DAC |
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