參數(shù)資料
型號(hào)： UDA1345
廠商： NXP Semiconductors N.V.
元件分類： Codec
英文描述： Economy audio CODEC
中文描述： 經(jīng)濟(jì)音頻CODEC
文件頁數(shù)： 9/28頁
文件大小： 126K
代理商： UDA1345
2000 Apr 18
9
Philips Semiconductors
Preliminary specification
Economy audio CODEC
UDA1345TS
L3 microcontroller mode
The UDA1345TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in Section
“L3 interface”.
P
INNING DEFINITION
The pinning definition under L3 microcontroller interface is
given in Table 5.
Table 5
Pinning definition under L3 control
S
YSTEM CLOCK
Under L3 control the options are 256, 384 and 512f
s
.
M
ULTIPLE FORMAT INPUT
/
OUTPUT INTERFACE
The UDA1345TS supports the following data input/output
formats under L3 control:
I
2
S-bus with data word length of up to 24 bits
MSB-justifiedserial formatwith datawordlength ofupto
20 bits
LSB-justified serial format with data word lengths of
16, 18 or 20 bits
Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
ADC
INPUT VOLTAGE CONTROL
The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 k
as described in Section “Analog
front-end”. In L3 microcontroller mode, the gain can be
selected via pin MP5.
When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.
O
VERLOAD DETECTION
(ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than
1 dB (the actual figure is
1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
s
cycles
(11.6 ms at f
s
= 44.1 kHz). This time-out is reset for each
infringement.
DC
CANCELLATION FILTER
(ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
themicrocontrollerviatheL3-bus.Thefiltercharacteristics
are given in Table 6.
Table 6
DC cancellation filter characteristics
Static pin mode
TheUDA1345TSissettostaticpincontrolmodebysetting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
P
INNING DEFINITION
The pinning definition under static pin control is given in
Table 7.
Table 7
Pinning definition for static pin control
SYMBOL
PIN
DESCRIPTION
MP1
MP2
MP3
MP4
MP5
9
13
14
15
20
OVERFL output
L3MODE input
L3CLOCK input
L3DATA input
ADC 1 or 2 V (RMS) input control
ITEM
CONDITIONS
VALUE (dB)
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
none
0
0.031
>40
>110
at 0.00045f
s
at 0.00000036f
s
0
0.45f
s
SYMBOL
PIN
DESCRIPTION
MP1
MP2
9
data input/output setting
3-level pin controlling de-emphasis
and mute
256f
s
or 384f
s
system clock
3-level pin to control ADC power
mode and 1 V (RMS) or 2 V (RMS)
input
data input/output setting
13
MP3
MP4
14
15
MP5
20
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UDA1345TS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Economy audio CODEC
UDA1345TS/N2 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, 28-SSOP
UDA1345TS/N2,112 功能描述:接口—CODEC AUDIO CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1345TS/N2,118 功能描述:接口—CODEC ECONOMY CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1345TS/N2118 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述:
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