2000 Feb 04
6
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
FUNCTIONAL DESCRIPTION
The UDA1344TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system clock must be
locked in frequency to the digital interface input signals.
The BCK clock can be up to 128f
s
, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
BCK
= < 128
×
f
WS
.
Remarks:
1.
The WS edge MUST fall on the negative edge of the
BCKclockatalltimesforproperoperationofthedigital
I/O data interface
2.
The sampling frequency range is from 5 to 55 kHz
3.
For MSB- and LSB-justified formats it is important to
have a WS signal with a duty factor of 50%.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1344TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input signals and can be set, via an external
resistor, to support 2 V (RMS) input signals.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block. The pin to select the gain switch is given
in Section “L3 mode”. This block can be used in
applications in which both 1 V (RMS) and 2 V (RMS) input
signals are available.
In applications in which a 2 V (RMS) input signal is used,
a 12 k
resistor must be connected in series with the input
of the ADC. This makes a voltage divider with the internal
ADC resistor and makes sure only 1 V (RMS) maximum is
input to the IC. Using this application for a 2 V (RMS) input
signal, the gain switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
againstthepresenceof anexternal resistorand thesetting
of the gain switch is given in Table 1.
Table 1
Application modes using input gain stage
Decimation filter (ADC)
The decimation from 128f
s
to 1f
s
is performed in 2 stages.
The first stage realizes 3rd-order
characteristic. This
filter decreases the sample rate by 16.
The second stage, a Finite Impulse Response (FIR) filter,
consists of 3 half-band filters, each decimating by a factor
of 2.
Table 2
Decimation filter characteristics
DC-cancellation filter (ADC)
AnoptionalInfiniteImpulse-Response(IIR)high-passfilter
is provided to remove unwanted DC components.
The operation is selected by the microcontroller via the
L3 interface. The filter characteristics are given in Table 3.
Table 3
DC-cancellation filter characteristics
RESISTOR
(12 k
)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present
Present
Absent
Absent
0 dB
6 dB
0 dB
6 dB
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
ITEM
CONDITIONS
0
0.45f
s
>0.55f
s
0
0.45f
s
DC
VALUE (dB)
±
0.05
60
108
1.16
Pass-band ripple
Stop band
Dynamic range
Overall gain with
0 dB input to the
ADC
ITEM
CONDITIONS
at 0.00045f
s
at 0.00000036f
s
0
0.45f
s
VALUE (dB)
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
none
0
0.031
>40
>110
sin x
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