參數(shù)資料
型號(hào)： UCC2919DTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝： GREEN, PLASTIC, MS-012AC, SOIC-16
文件頁(yè)數(shù)： 27/27頁(yè)
文件大小： 701K
代理商： UCC2919DTR
UCC2919
UCC3919
SLUS374C JULY 1999 REVISED NOVEMBER 2005
9
www.ti.com
APPLICATION INFORMATION
overload threshold
There is a third threshold which, if exceeded, will declare a fault and shutdown the external MOSFET
immediately, without waiting for CT to charge. This overload threshold is 200 mV greater than the IMAX threshold
(again, this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is
on, with a load current below IMAX, and a short is quickly applied across the output. This allows hot-swapping
in cases where the UCC3919 is already powered up (on the backplane) and capacitors are added across the
output bus. In this case, the load current could rise too quickly for the linear amplifier to reduce the voltage on
GATE and limit the current to IMAX. If the overload threshold is reached, the MOSFET will be turned off quickly
and a fault declared. A latch is set so that CT can be charged, ensuring that the MOSFET will remain off for the
same period as defined above before retrying. The overload current is:
I
OVERLOAD +
V
CSP *
V
IMAX )
0.2
R
SENSE
+ I
MAX )
0.2
R
SENSE
Note that IOVERLOAD may be much greater than IMAX, depending on the value of RSENSE.
power limiting
A power limiting feature is included which allows the power dissipated in the external MOSFET to be held
relatively constant during a short, for different values of input voltage. This is accomplished by connecting a
resistor from the output (source of the external MOSFET) to PL. When the output voltage drops due to a short
or overload, an internal bias current is generated which is equal to:
I
PL ^
V
IN *
V
OUT *
V
PL
R
PL
This current is used to help charge the timing capacitor in the event that the load current exceeds IFAULT. (A
simplified schematic of the circuit internal to the UCC3919 is shown in Figure 2.) The result is that the on time
of the MOSFET during current limit is reduced as the input voltage is increased. This reduces the effective duty
cycle, holding the average power dissipated constant.
RPL
CT
VDD
UCC3919
POWER LIMIT
1X
TO
GATE
TO
LOAD
VDD
SD
PL
FLT
IPL
UDG98124
Figure 2. Power Limiting Circuit
(6)
(7)
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