參數(shù)資料
型號(hào): U634H256CD1K25
英文描述: NVRAM (EEPROM Based)
中文描述: NVRAM中(EEPROM的基礎(chǔ))
文件頁(yè)數(shù): 2/14頁(yè)
文件大?。?/td> 239K
代理商: U634H256CD1K25
2
December 12, 1997
U634H256
EEPROM
Array
STORE
RECALL
SRAM
Array
512 Rows x
64 x 8 Columns
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 - A13
Store/
Control
HSB
R
V
CCX
V
SS
V
CAP
G
E
W
A0 A1
A2 A3 A4A10
Software
Detect
Power
Control
V
CCX
V
CAP
A5
A6
A7
A8
A9
A11
A12
A13
A14
I
Operating Mode
E
HSB
W
G
DQ0 - DQ7
Standby/not selected
H
H
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read
L
H
H
L
Data Outputs Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table for SRAM Operations
Block Diagram
a:
Stresses greater than those listed under Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.3
V
CC
+0.5
V
Output Voltage
V
O
-0.3
V
CC
+0.5
V
Power Dissipation
P
D
1
W
Operating Temperature
C-Type
K-Type
T
a
0
-40
70
85
°
C
°
C
Storage Temperature
T
stg
-65
150
°
C
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
*
H or L
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