參數(shù)資料
型號(hào): TXN132204015A45
廠商: INTEL CORP
元件分類: 光收發(fā)
英文描述: FIBER OPTIC TRANSCEIVER, TRANSPONDER, 1530-1565nm, 10000Mbps(Tx), 10000Mbps(Rx), MU CONNECTOR
封裝: ROHS COMPLIANT, PACKAGE-300
文件頁數(shù): 24/52頁
文件大小: 1394K
代理商: TXN132204015A45
Intel TXN13220/1/4/5/7/8 SFF 10 Gbps Optical Transceiver
Intel TXN13220/1/4/5/7/8 SFF 10 Gbps Optical Transceiver
Datasheet
26-Oct-2006
30
Order Number: 273807004
Table 32. Digital Alarms
Function
Pin Name
Pin
Num-
ber
Logic Logic 0 Logic 1
Condition
Transmitter PLL
lock error
TxLOCKERR
B30
LVTTL Out of
lock
In lock
Out of lock when on chip VCO not
locked to TxREFCLK
Receiver PLL
lock detect
RxLOCKERR
B15
LVTTL Out of
lock
In lock
Low if CDR is unable to recover
valid clock from receive optical
input signal.
Receiver loss of
average power
alarm
RxPOWALM
F6
LVTTL Noinput
signal
Input
signal
present
Logic high for signal above
receiver sensitivity. Low for signal
< -30 dBm.
Laser bias
alarm
LsBIASALM
F24
LVTTL Alarm
Normal
Alarm if laser bias >100 mA
Laser temp
alarm
LsTEMPALM
F27
LVTTL Alarm
Normal
Alarm if laser temperature
deviates more than 2.5 degrees
from initial set point
Receiver alarm
interrupt
RxALMINT
J14
LVTTL Alarm
Normal
Electrical OR of all receive alarms
Alarm interrupt ALMINT
H15
LVTTL Alarm
Normal
Electrical OR of all receive and
transmit alarms
Transmitter
alarm interrupt TxALMINT
J16
LVTTL Alarm
Normal
Electrical OR of all transmit alarms
Table 33. Digital Control Signals and I2C Bus
Function
Pin Name
Pin
Num-
ber Logic
Logic 0
Logic 1
Transmitter laser enable in
LsENABLE
F21
LVTTL
Enabled
Disabled
Selects 1/64 line bit rate or 1/16 line bit
rate-MHz reference clock for mux -
TxREFCLK
TxREFSEL
F30
LVTTL 1/64 line bit
rate MHz
1/16 line bit
rate MHz
Selects 1/64 line bit rate or 1/16 line bit
rate of reference clock for demux -
RxREFCLK
RxREFSEL
F15
LVTTL 1/64 line bit
rate
1/16 line bit
rate
Selects 1/64 line bit rate or 1/16 line bit
rate of demux monitor clock out - RxMCLK
RxMCLKSEL
B12
LVTTL 1/64 line bit
rate
1/16 line bit
rate
Line timing mode internally loops
recovered receive clock (RxPOCLK) back to
TxREFCLK
TxLINETIMSEL H30
LVTTL Line Timing
TxREFCLK
Timing
Receive lock to reference forces the VCO in
the receiver clock recovery circuit to lock
to RxREFCLK
RxLCKREF
B9
LVTTL
Lock to ref
Normal
Mutes the data outputs of the demux
RxMuteDout
B6
LVTTL
Mutes the
RxDout
[0:15]
Normal
Mutes the RxPOCLK
RxMutePOCLK
K9
LVTTL
Mutes the
RxPOCLK
Normal
I2C Clock Input
I2CCLOCK
K15
LVTTL
I2C Data
I2CDATA
K18
LVTTL
TxRATESEL1
TxRateSel1
J21
LVTTL See Table 34 See Table 34
TxRATESEL0
TxRateSel0
K21
LVTTL See Table 34 See Table 34
See the application note for details regarding the contents of the EEPROM.
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