參數(shù)資料
型號(hào)： TWL2213CAPFBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 6/33頁(yè)
文件大?。?/td> 498K
代理商： TWL2213CAPFBR
TWL2213CA
POWER SUPPLY MANAGEMENT IC AND
Li-Ion BATTERY CHARGE CONTROL
SLVS280 – MARCH 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C bus protocols
The TWL2213 serial interface is designed to be I2C bus compatible, operating in the slave mode. This interface
consists of the following terminals:
CLK: I2C bus serial clock. This input synchronizes the control data transfer from and to the microprocessor.
DATA: I2C bus serial address/data input/output. This is a bidirectional terminal that transfers registers,
control addresses, and data into and out of the microprocessor. This terminal is an open drain and requires a
pullup resistor of 10 k
to VREG1.
The TWL2213 device has a fixed device select addresses of E4h for write mode and E5h for read mode. For
normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved
for indicating the start and stop conditions. Data transfer may be initiated only when the bus is not busy (both
DATA and CLK lines remain high). During data transfer, the data line must remain stable whenever the clock
line is at high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and
terminated with a stop condition. When addressed, the TWL2213 device generates an acknowledge after the
reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is
associated with the acknowledge bit. The TWL2213 device must pull down the DATA line during the
acknowledge clock pulse so that the DATA line is at stable low state during the high period of the acknowledge
clock pulse. The DATA line is at a stable low state during the high period of the acknowledge related clock pulse.
Setup and hold times must be taken into account. During read operations, a master must signal the end of data
to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case,
the slave TWL2213 device must leave the data line high to enable the master to generate the stop condition.
Data Line
Stable;
Data Valid
DATA
CLK
Change
of Data
Allowed
Figure 4. Bit Transfer on the I2C Bus
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TWL2214CA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Supply Management IC and Li-Ion Battery Charge Control
TWL2214CAPFB 制造商:Rochester Electronics LLC 功能描述:POWER SUPPLY MANAGEMENT IC:LION - Bulk 制造商:Texas Instruments 功能描述:CHGR LI-ION/LI-POL 150MA 2.8V 48TQFP - Tape and Reel
TWL2214CAPFBR 制造商:Rochester Electronics LLC 功能描述:POWER SUPPLY MANAGEMENT IC:LION - Bulk 制造商:Texas Instruments 功能描述:CHGR LI-ION/LI-POL 150MA 2.8V 48TQFP - Tape and Reel
TWL2217CGGMR 制造商:Texas Instruments 功能描述:
TWL2217CZQER 制造商:Texas Instruments 功能描述:
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