參數(shù)資料
型號(hào): TWL1106PWR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO20
封裝: PLASTIC, TSSOP-20
文件頁(yè)數(shù): 5/19頁(yè)
文件大小: 260K
代理商: TWL1106PWR
TWL1106
VOICEBAND AUDIO PROCESSOR (VBAP)
SLWS094 – JUNE 2001
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive volume control
In linear mode, RXVOL [2:0] PCM data bits are used for volume control according to Table 3. Volume control
bits must be sent on PCMI for each 13-bit receive word. In companded mode, volume control is fixed at 0 dB.
Table 3. Volume Control Bit Definition in Linear Mode
RXVOL [2:0]
GAIN SETTING
000
3 dB
001
0 dB
010
–3 dB
011
–6 dB
100
–9 dB
101
–12 dB
110
–15 dB
111
–18 dB
support section
The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and converters.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate. The PCMSYN signal must be derived from the
master clock. The divide ratio must be set to 256 for the device to work properly.
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