參數(shù)資料
型號(hào)： TWL1106PWR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 19/19頁(yè)
文件大?。?/td> 260K
代理商： TWL1106PWR
TWL1106
VOICEBAND AUDIO PROCESSOR (VBAP)
SLWS094 – JUNE 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
power supply rejection
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
MICIN–, MICIN+ = 0 V,
VDD = 2.7 V + 100 mVpp, f = 1 kHz,
Resistor tolerance of 1%
–74
–50
dB
Supply voltage rejection, receive channel
(differential)
PCM code = positive zero,
VDD = 2.7 V + 100 mVpp, f = 1 kHz,
Resistor tolerance of 1%
–80
–65
dB
crosstalk attenuation, linear mode selected
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Crosstalk attenuation, transmit-to-receive
(differential)
MICIN–, MICIN+ = 0 dB, f = 300 Hz to 3400 Hz
measured differentially between EAROUT– and
EAROUT+
70
dB
Crosstalk attenuation, receive-to-transmit
PCMI = 0 dBm0, f = 300 Hz to 3400 Hz measured at
PCMO
70
dB
timing requirements
clock
MIN
NOM
MAX
UNIT
tt
Transition time, MCLK
10
ns
fmclk
MCLK frequency
2.048
MHz
MCLK jitter
37%
MCLK clock cycles per PCMSYN frame
256
cycles
transmit (see Figure 1)
MIN
MAX
UNIT
tsu(PCMSYN)
Setup time, PCMSYN high before MCLK
↓
20
tc(MCLK)–20
ns
th(PCMSYN)
Hold time, PCMSYN high after MCLK
↓
20
tc(MCLK)–20
receive (see Figure 2)
MIN
MAX
UNIT
tsu(PCSYN)
Setup time, PCMSYN high before MCLK
↓
20
tc(MCLK)–20
ns
th(PCSYN)
Hold time, PCMSYN high after MCLK
↓
20
tc(MCLK)–20
ns
tsu(PCMI)
Setup time, PCMI high or low before MCLK
↓
20
ns
th(PCMI)
Hold time, PCMI high or low after MCLK
↓
20
ns
switching characteristics over recommended operating conditions, CLmax = 10 pF (see Figure 1)
TEST CONDITIONS
MIN
MAX
UNIT
tpd1
Propagation delay time, MCLK bit 1 high to PCMO bit 1 valid
35
ns
tpd2
Propagation delay time, MCLK high to PCMO valid, bits 2 to n
35
ns
tpd3
Propagation delay time, MCLK bit n low to PCMO bit n Hi-Z
30
ns
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