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| 型號： | TVP7002PZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 13/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZP |
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SLES206B
– MAY 2007 – REVISED MAY 2011
Embedded Syncs
Standard embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges of
AVID. These codes contain the V and F bits that also define vertical timing. Table 7 gives the format of the SAV
and EAV codes.
H = 1 always indicates EAV. H = 0 always indicates SAV. The alignment of V and F to the line and field counter
varies depending on the standard. The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 7. EAV and SAV Sequence
Y9 (MSB)
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Preamble
1
Preamble
0
Preamble
0
Status
1
F
V
H
P3
P2
P1
P0
0
The pixel locations where SAV/EAV embedded sync codes are inserted can be programmed using the AVID
Start Pixel and AVID Stop Pixel I2C registers. The AVID start location is determined from the HSYNC interval,
horizontal back porch interval (Hbp) and a digital process delay factor (PDELAY) required for compensation of
internal TVP7002 delays. An additional four bytes must be added to the active pixel interval between AVID start
and AVID stop to accommodate embedded sync insertion.
AVID Start Pixel = PDELAY + HSYNC + Hbp
AVID Stop Pixel = AVID Start Pixel + Active Pixels + 4
NOTE
Some AVID Stop Pixel calculations will exceed the HPLL-Feedback Register setting, or
total pixels per line. When this occurs, subtract total pixels per line from AVID Stop Pixel.
NOTE
DELAY is typically 27 pixels but may vary slightly depending on other TVP7002 settings
such as the Sync-on-Green Threshold setting (I2C register 10h) and the SOG LPF setting
(I2C register 1Ah).
The line numbers where the embedded V-bit and F-bit occur are controlled by I2C registers 44h to 49h, which
define the vertical blanking interval and field start positions. See Table 8 for typical embedded syncs settings.
Table 8. Typical Embedded Sync Settings
VBLK
F-bit
Output
AVID Start Pixel
AVID Stop Pixel
Field 0
Field 1
Field O
Field 1
Field 0
Field 1
Input Format
Format
Start Line
Duration
Start Line
REG 15h
REG 41h
REG 40h
REG 43h
REG 42h
REG 44h
REG 45h
REG 46h
REG 47h
REG 48h
REG 49h
480i60Hz
47h
00h
95h
00h
0Fh
01h
13h
02h
01h
480p60Hz
47h
00h
93h
00h
0Dh
09h
2Dh
00h
720p60Hz
47h
01h
47h
06h
4Bh
05h
1Eh
00h
1080i60Hz
47h
01h
07h
08h
8Bh
02h
16h
17h
00h
1080p60Hz
47h
01h
07h
08h
8Bh
04h
2Dh
00h
20
Copyright
2007–2011, Texas Instruments Incorporated
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| TVP7002PZPR | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8/10B 165/110MSPS Video ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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| TVP9000ZDS | 制造商:Texas Instruments 功能描述: |
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