參數(shù)資料
型號(hào)： TVP7001PZPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 3/35頁
文件大小： 504K
代理商： TVP7001PZPR
www.ti.com
COAST
HSYNC
Phase
Detector
PLL Control
Register 0x03
Bit [5:3]
PLL Control
Register 0x03
Bit [7:6]
Phase Select
Register 0x04
Bit [7:3]
Charge
Pump
VCO
Phase
Select
Divider
ADC
Sampling
CLK
External
Clock
PLL Divide
Register 0x01
and 0x02
Bit [11:0]
Loop
Filter
÷ N
N = 1 or 2
SLES164 – FEBBRUARY 2006
Analog PLL
The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to
derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal
sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded
sync signals. The analog PLL consisted of phase detector, loop filter, voltage controlled oscillator (VCO), divider
and phase select. The analog block diagram is shown at Figure 3.
Figure 3. PLL Block Diagram
The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the
incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other
time that the HSYNC is not available.
There are several PLL controls to produce the correct sampling clock. The 12-bit divider register is
programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to 165
MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass
loop filter. The applicable current values are listed in the Table 1.
The 2-bit VCO range control is to improve the noise performance of the TVP7001. The frequency ranges for the
VCO are shown in Table 1. The phase of the PLL generated clock can be programmed in 32 uniform steps over
a single clock period (360/32=11.25 degrees phase resolution) so that the sampling phase of the ADC can be
accurately controlled.
In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from pin 80).
The PLL characteristics are determined by the loop filter design, by the PLL charge pump current, and by the
VCO range setting. The loop filter design is shown in Figure 4. Supported settings of VCO range and charge
pump current for VESA standard display modes are listed in Table 1.
11
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