參數(shù)資料
型號： TVP6000CPFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL ENCODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 13/57頁
文件大?。?/td> 268K
代理商： TVP6000CPFP
2–8
2.5.3
Cross Color Reduction Filter
An optional cross color reduction filter can be applied to the luminance signal before the luminance signal
combines with the chrominance signal to form the composite signal. The cross color reduction filter reduces
the interference between the luminance and chrominance in the composite signal. The cross reduction filter
does not apply to S-video.
2.5.4
Chrominance Encoding
The time-multiplexed U/V signal is adjusted by a pair of programmable gains. The gain for U and the gain
for V are independently controlled by the GAIN_U and GAIN_V register bits respectively at subaddresses
5B, 5C, 5D, and 5E. The gain-adjusted signal then passes through a chrominance low-pass filter to limit the
bandwidth of the U/V signal. The chrominance low-pass filter can be optionally bypassed by setting the CBW
bit of the M_CONTROL register at subaddress 61 to 0. This setting enlarges the bandwidth on U/V for
S-video output.
The low-passed U/V signal is then subjected to a 1-to-4 interpolation through an interpolation filter. The data
rate for both U and V is now at a 2x pixel rate.
The U and V signals are then quadrature-modulated by the internally generated subcarrier signal to form
the chrominance (C) signal. The subcarrier reference signal color burst is inserted right before the active
video.
The frequency, the phase of the modulating subcarrier, and the amplitude of the color burst are all
programmable. When genlock is disabled (the GLCE bit of the M_CONTROL register set to 0), the
subcarrier frequency is controlled by the S_CARR registers at subaddresses 63, 64, 65, and 66. The values
of the registers are computed based on the desired subcarrier frequency and the LLC clock using the
equation in the register description. Table 2–12 lists the most commonly used values for various standards.
When genlock is enabled (GLCE set to 1), the subcarrier frequency is updated once every scan line using
the frequency control bits serially shifted in at the GLCI pin.
The C_PHASE register at subaddress 5A controls the phase of the subcarrier. The phase of the color
subcarrier is reset to C_PHASE when enabled. Four modes of color subcarrier reset are provided: reset
every two lines, every two fields, every eight fields, or at a reset bit input at the GLCI pin if genlock is enabled.
Users can use the C_PHASE register to adjust the subcarrier-to-horizontal sync phase. The bits BSTAP[6:0]
of the BSTAMP register at subaddress 62 sets the amplitude of the color burst. The PAL bit of the
M_CONTROL register enables phase alternation line encoding. A sweeping subcarrier is generated to
encode the chrominance signal when the PAL bit is set to 1. Otherwise a normal subcarrier is generated.
Phase alternation line refers to an encoding scheme in which the subcarrier alternates between two different
phases every scan line. There are two possible alternate sequences and the PALPHS bit of the
M_CONTROL register selects one of the sequences.
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