參數(shù)資料
型號: TVP5154PNPRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: PLASTIC, HTQFP-128
文件頁數(shù): 40/77頁
文件大?。?/td> 795K
代理商: TVP5154PNPRG4
www.ti.com
9.2.43
ROM Minor Version Register
9.2.44
Vertical Line Count MSB Register
9.2.45
Vertical Line Count LSB Register
9.2.46
Interrupt Status Register B
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Address
83h
Default
00h
7
6
5
4
3
2
1
0
ROM minor version(1)
(1)
This register can contain a number from 0x01 to 0xFF.
Address
84h
7
6
5
4
3
2
1
0
Reserved
Vertical line count MSB
Vertical line count bits [9:8]
Address
85h
7
6
5
4
3
2
1
0
Vertical line count LSB
Vertical line count bits [7:0]
Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This
can be used with nonstandard video signals, such as a VCR in fast-forward or rewind modes, to
synchronize the downstream video circuitry.
Address
86h
7
6
5
4
3
2
1
0
Software
Reserved
Command
Field rate
Line alternation
Color lock
H/V lock
TV/VCR
initialization
ready
changed
Software initialization:
0 = Software initialization is not ready (default).
1 = Software initialization is ready.
Command ready:
0 = TVP5154 is not ready to accept a new command (default).
1 = TVP5154 is ready to accept a new command.
Field rate changed:
0 = Field rate has not changed (default).
1 = Field rate has changed.
Line alternation changed:
0 = Line alteration has not changed (default).
1 = Line alternation has changed.
Color lock changed:
0 = Color lock status has not changed (default).
1 = Color lock status has changed.
H/V lock changed:
0 = H/V lock status has not changed (default).
1 = H/V lock status has changed.
TV/VCR changed:
0 = TV/VCR status has not changed (default).
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt
B. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at
subaddress 1Ch with a 1 in the appropriate bit.
Internal Control Registers
45
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