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5.1 I2C Write Operation
5.2 I2C Read Operation
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Note, when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when register
0xFF is written to with any value, register 0xFE is set to 0x00.
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5154 decoder by generating a start condition (S)
followed by the TVP5154 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate
a write cycle. After receiving an acknowledge from the TVP5154 decoder, the master presents the
sub-address of the register, or the first of a block of registers it wants to write, followed by one or more
bytes of data, MSB first. The TVP5154 decoder acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition (P).
abc
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
1
0
1
0
X
0
Step 3
9
I2C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C write register address (master)
addr
Step 5
9
I2C acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
I2C write data (master)
Data
Step 7(1)
9
I2C acknowledge (slave)
A
Step 8
0
I2C stop (master)
P
(1)
Repeat steps 6 and 7 until all data have been written.
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP5154 decoder by generating a start condition (S) followed by
the TVP5154 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledges from the TVP5154 decoder, the master presents the sub-address of the register or the first
of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle
immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an IC master initiates a read operation to the
TVP5154 decoder by generating a start condition followed by the TVP5154 I2C address (as shown below
for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge
from the TVP5154 decoder, the I2C master receives one or more bytes of data from the TVP5154
decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte
desired has been transferred from the TVP5154 decoder to the master, the master generates a not
acknowledge followed by a stop.
16
I2C Host Interface