參數(shù)資料
型號(hào): TVP5154PNPR
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: GREEN, PLASTIC, HTQFP-128
文件頁(yè)數(shù): 49/79頁(yè)
文件大?。?/td> 908K
代理商: TVP5154PNPR
www.ti.com
9.2.62 Interrupt Configuration Register A
9.2.63 VDP Configuration RAM Register
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Address
C2h
Default
04h
7
6
5
4
3
2
1
0
Reserved
YCbCr enable (VDPOE)
Interrupt A
Interrupt polarity A
YCbCr enable (VDPOE):
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read only):
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A:
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When
interrupt A is configured as active low, the terminal is driven low when active and high impedance when
inactive (open collector). Conversely, when the terminal is configured as active high, it is driven high when
active and driven low when inactive.
Address
C3h
C4h
C5h
Default
B8h
1Fh
00h
Address
7
6
5
4
3
2
1
0
C3h
Configuration data
C4h
RAM address (7:0)
C5h
Reserved
RAM address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM
is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are
defined for the current VBI standards. An additional two configurations can be used as a custom
programmed mode for unique standards, such as Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically
incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal
address counter with a specific start address. This can be used to write a subset of the RAM for only
those standards of interest. Registers D0h–FBh must all be programmed with FFh before writing or
reading the configuration RAM. Full field mode (CFh) must be disabled as well.
The suggested RAM contents are shown in the following table. All values are hexadecimal.
Internal Control Registers
53
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