參數(shù)資料
型號： TVP5154AIPNPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： PLASTIC, HTQFP-128
文件頁數(shù)： 25/92頁
文件大?。?/td> 1089K
代理商： TVP5154AIPNPR
www.ti.com
SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
7.2.4
Miscellaneous Control Register
Address
03h
Default
01h
7
6
5
4
3
2
1
0
VBKO
GPCL pin
GPCL output
Lock status
YCbCr output
HSYNC, VSYNC/PALI,
Vertical blanking
CLK output
enable
(HVLK)
enable(TVPOE)
AVID, FID/GLCO output
on/off
enable
VBKO (pins 41, 60, 83, 102) function select:
0 = GPCL (default)
1 = VBLK
Note, if these pins are not configured as outputs, they must not be left floating. A 10-k
pulldown resistor is recommended if
not driven externally.
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable:
0 = GPCL is inactive (default). GPCL should not be programmed to 0 when register 0Fh bit 1 is 1 (programmed to be
GPCL/VBLK).
1 = GPCL is output.
Note that, if these pins are not configured as outputs, they must not be left floating. A 10-k
pulldown resistor is
recommended if not driven externally.
Lock status (HVLK) (configured along with register 0Fh, see Figure 7-1 for the relationship between the configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field ID (FID) signal
(default) (if terminals are configured to output PALI and FID in register 0Fh).
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical lock indicator (VLK) (if
terminals are configured to output PALI and FID in register 0Fh).
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
Note, if these pins are not configured as outputs, they must not be left floating. A 10-k
pulldown resistor is recommended if
not driven externally.
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Note, if these pins are not configured as outputs, they must not be left floating. A 10-k
pulldown resistor is recommended if
not driven externally.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
CLK output enable:
0 = CLK output is high impedance.
1 = CLK output is enabled (default).
Note: CLK edge and SCLK are configured through register 05h.
Table 7-3. Digital Output Control
REGISTER 03h,
REGISTER C2h,
YCbCr OUTPUT
BIT 3 (TVPOE)(1)
BIT 2 (VDPOE)(1)
0
X
High impedance
X
0
High impedance
1
Active
(1)
VDPOE default is 1 and TVPOE default is 0.
Copyright 2007–2010, Texas Instruments Incorporated
Internal Control Registers
31
Product Folder Link(s): TVP5154A
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TVP5154APNP 功能描述:視頻 IC 4Ch Lo Pwr PAL/NTSC SECAM Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TVP5154APNPR 功能描述:視頻 IC 4Ch Lo Pwr PAL/NTSC SECAM Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TVP5154EVM 功能描述:視頻 IC 開發(fā)工具 TVP5154 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V
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