參數(shù)資料
型號(hào): TVP5146M2PFPRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: GREEN, PLASTIC, HTQFP-80
文件頁(yè)數(shù): 93/107頁(yè)
文件大小: 1427K
代理商: TVP5146M2PFPRG4
Functional Description
78
SLES141B—August 2007
TVP5146M2PFP
2.11.95 Interrupt Clear 0 Register
Subaddress
F6h
Default
00h
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS
VPS
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed clear
0 = No effect (default)
1 = Clear bit 7 (FIFO_THRS) in the interrupt status 0 register at subaddress F2h
TTX: Teletext data available clear
0 = No effect (default)
1 = Clear bit 6 (TTX available) in the interrupt status 0 register at subaddress F2h
WSS: WSS data available clear
0 = No effect (default)
1 = Clear bit 5 (WSS available) in the interrupt status 0 register at subaddress F2h
VPS: VPS data available clear
0 = No effect (default)
1 = Clear bit 4 (VPS available) in the interrupt status 0 register at subaddress F2h
VITC: VITC data available clear
0 = Disabled (default)
1 = Clear bit 3 (VITC available) in the interrupt status 0 register at subaddress F2h
CC F2: CC field 2 data available clear
0 = Disabled (default)
1 = Clear bit 2 (CC field 2 available) in the interrupt status 0 register at subaddress F2h
CC F1: CC field 1 data available clear
0 = Disabled (default)
1 = Clear bit 1 (CC field 1 available) in the interrupt status 0 register at subaddress F2h
Line: Line number interrupt clear
0 = Disabled (default)
1 = Clear bit 0 (line interrupt available) in the interrupt status 0 register at subaddress F2h
See also the interrupt clear 1 register at subaddress F7h (see Section 2.11.96).
The host interrupt clear 0 and 1 registers are used by the external processor to clear the interrupt status bits
in the host interrupt status 0 and 1 registers. When no nonmasked interrupts remain set in the registers, the
external interrupt terminal also becomes inactive.
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TVP5146M2PFPG4 COLOR SIGNAL DECODER, PQFP80
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